The present invention relates generally to a method for manufacturing a semiconductor device, and, more particularly, to a method for manufacturing a semiconductor device having a low-resistance gate electrode.
From the initial stages of development of VLSI (Very Large Scale Integration) technology to the present, gate electrodes made of polysilicon have been employed because of their advantageous electrical characteristics, reliability, and packing density. Further, since polysilicon is a refractory material, it is possible to use the polysilicon gate electrode to simultaneously form self-aligned source/drain diffusion regions of the semiconductor device in a precise manner. This self-aligned gate process technology facilitates easier and more efficient manufacturability of the semiconductor device, and enhances the performance and reliability of the semiconductor device. Additionally, since polysilicon can be thermally oxidized after being patterned into a gate electrode, it is possible to smooth the edges of the gate electrode which are susceptible to damage caused by reactive ion etching, and, at the same time, to alleviate fringe electric fields at the edges of the gate electrode, thereby further enhancing the reliability of the semiconductor device. For these reasons, polysilicon gate electrodes are widely used in the vast majority of VLSI chips, including high-density memory chips (e.g., DRAMs and SRAMs) and other chips used in computers and a wide variety of products.
However, in ULSI (Ultra Large Scale Integration) devices having sub-micron geometries (i.e., manufactured using a design rule of&lt;1&lt;1 .mu.m), the polysilicon gate structure nullifies the increased device operational speed obtained by virtue of the higher packing densities characteristic of ULSI devices. In this regard, the polysilicon gate structure induces delays in signal transmission due to an increase in the wiring resistance of the device as a consequence of its miniaturization, and an increase in the wiring capacitance as a consequence of the reducing wiring pitch.
For these reasons, alternative materials to polysilicon, such as refractory silicides are now being used in some ULSI devices, because of their much lower resistance than polysilicon. In fact, some refractory silicides, such as tungsten silicide/n.sup.+ polysilicon, has a greater than one order of magnitude (i.e., more than one decimal place) lower resistance than polysilicon.
With reference now to FIGS. 1A, 1B, and 1C, there can be seen cross-sectional views depicting successive steps of a method for manufacturing a semiconductor device utilizing the tungsten silicide/n.sup.+ polysilicide gate electrode technology.
With reference now to FIG. 1A, a gate insulating layer 2 is formed on a semiconductor substrate I by way of a thermal oxidation process. An n.sup.+ doped polysilicon layer 3 is formed on the gate insulating layer 2 to a thickness of 500-5,000 angstroms. Next, a tungsten silicide layer 4 is formed on the doped polysilicon layer 3, and then, an oxide layer 5 is formed on the tungsten silicide layer 4.
With reference now to FIG. 1B, a photoresist pattern 6 for defining a gate electrode is formed on the oxide layer 5, by way of a standard photolithograhic process.
With reference now to FIG. 1C, using the photoresist pattern 6 as an etching mask, the oxide layer 5, tungsten silicide layer 4, and polysilicon layer 3 are sequentially etched, by way of a standard reactive ion etching process, and then, the photoresist is removed, to thereby leave a gate electrode comprised of the tungsten silicide layer 4 and the n.sup.+ polysilicon layer 3.
The above-described method for forming a tungsten silicide/n.sup.+ polysilicon gate electrode is simpler and produces a much lower resistance gate electrode than the conventional method for forming a polysilicon gate electrode. However, the above-described method for forming a tungsten silicide/n.sup.+ polysilicon gate electrode is disadvantageous in that a thermal oxidation process can not be performed to compensate for damage to the gate electrode caused by subsequent reactive ion etching steps of the overall process for manufacturing the semiconductor device of which the gate electrode is a part. In this regard, if the exposed portion of the tungsten silicide layer is subjected to thermal oxidation, it becomes highly degraded due to the volume expansion thereof, as can be seen in the SEM photograph of FIG. 2. If thermal oxidation step is omitted in order to avoid such problems, the gate insulating layer becomes highly degraded due to damage occasioned by the reactive ion etching step for patterning the gate electrode. Moreover, when voltage is applied to the gate electrode, the fringe electric field created at the edges of the gate electrode is increased, thus degrading the breakdown voltage characteristic of the gate insulating layer, which can cause malfunction of the entire semiconductor device.
Based on the above and foregoing, it can be appreciated that there presently exists a need in the art for a method for manufacturing a semiconductor device having a low-resistance gate electrode which eliminatges the above-described drawbacks and shortcomings of the presently available technology. The present invention fulfills this need.